6.1 Wafer-level packaging techniques
3 min read•august 7, 2024
Wafer-level packaging is a game-changer for MEMS and NEMS devices. It shrinks package size, boosts performance, and cuts costs by packaging devices before they're cut into individual chips. This approach is key to making tiny, powerful gadgets.
From chip-scale packaging to thin film encapsulation, these techniques are revolutionizing how we protect and connect microdevices. They're paving the way for smaller, faster, and more reliable tech in everything from smartphones to medical implants.
Wafer-level Packaging Techniques
Overview of Wafer-level Packaging
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- Wafer-level packaging (WLP) packages MEMS/NEMS devices at the wafer level before singulation into individual chips
- WLP offers advantages such as reduced package size, improved , and lower cost compared to traditional packaging methods
- WLP processes include wafer-level bonding, patterning, and solder bump formation
- Chip-scale packaging (CSP) is a type of WLP where the package size is not much larger than the chip itself (typically within 20% of the chip size)
Wafer-level Chip-scale Packaging and Thin Film Encapsulation
- Wafer-level chip-scale packaging (WLCSP) is a specific type of CSP where the package is fabricated directly on the wafer before singulation
- WLCSP eliminates the need for wire bonding or flip chip assembly, reducing package size and improving electrical performance
- WLCSP processes include wafer-level redistribution layer (RDL) patterning, under-bump metallization (UBM), and solder bump formation
- Thin film encapsulation is a WLP technique that deposits a thin protective layer (such as silicon nitride or polyimide) over the MEMS/NEMS devices to provide hermetic sealing and protection from the environment (moisture, particles, etc.)
Interconnect and Bonding Technologies
Through-silicon Vias and Redistribution Layers
- are vertical electrical connections that pass completely through a or die, enabling 3D integration of MEMS/NEMS devices
- TSVs allow for shorter interconnect lengths, reduced parasitic capacitance, and improved bandwidth compared to traditional wire bonding
- TSV fabrication involves etching deep holes in the silicon, depositing an insulating layer (oxide or nitride), and filling the holes with conductive material (copper or tungsten)
- Redistribution layer (RDL) is a metal interconnect layer that redistributes the bond pads on a chip to a larger pitch, allowing for easier bonding and packaging
- RDL is typically fabricated using thin film deposition (sputtering or evaporation) and photolithography processes
Wafer Bonding Techniques
- is a process that joins two or more wafers together to form a single stack, enabling 3D integration and hermetic sealing of MEMS/NEMS devices
- Common wafer bonding techniques include (direct bonding), , , and adhesive bonding
- Fusion bonding involves bringing two clean, flat wafer surfaces into contact and applying high temperature (typically >1000°C) to form a strong covalent bond between the wafers
- Anodic bonding uses an applied electric field and moderate temperature (300-500°C) to create a bond between a silicon wafer and a glass wafer containing mobile ions (sodium or lithium)
- Eutectic bonding uses a low-melting-point alloy (such as gold-tin or gold-silicon) to form a bond between two wafers at a relatively low temperature (<400°C)
Advanced Packaging Methods
Cavity Packaging Techniques
- is a method that creates a sealed cavity around the MEMS/NEMS device to protect it from the environment and allow for free movement of mechanical structures
- Cavity packaging can be achieved through wafer-level processes such as wafer bonding or
- Sacrificial layer etching involves depositing a temporary material (such as or polyimide) over the MEMS/NEMS device, bonding a capping wafer, and then removing the sacrificial layer through etching to create the cavity
- Wafer-level cavity packaging offers advantages such as reduced package size, improved reliability, and lower cost compared to traditional cavity packaging methods (ceramic or metal packages)
- Examples of MEMS devices that require cavity packaging include accelerometers, gyroscopes, and microphones, where the mechanical structures need to be free to move within the sealed cavity
Key Terms to Review (24)
Anodic Bonding: Anodic bonding is a method used to create a strong, permanent bond between a silicon wafer and a glass substrate by applying a high electric field and heat. This technique is particularly useful in microfabrication, allowing for the integration of electrical components with optical elements. The process leads to improved device performance and reliability, making it essential in areas such as surface and bulk micromachining, wafer-level packaging, and hermetic sealing.
Cavity packaging: Cavity packaging is a method used to encapsulate microelectromechanical systems (MEMS) and other electronic components within a defined cavity that provides protection and structural support. This technique helps in minimizing the overall size of the package while enhancing performance by offering better thermal management and mechanical stability, which are essential for the reliability of sensitive devices.
Die bonding: Die bonding is the process of attaching a semiconductor die to a substrate, which is crucial for the functionality and reliability of microelectronic devices. This technique ensures that the electrical connections between the die and the substrate are established, while also providing mechanical stability. Die bonding can significantly influence the performance characteristics of devices, especially in wafer-level packaging, where minimizing space and maximizing efficiency are key objectives.
Electrical performance: Electrical performance refers to the ability of a device or system to effectively conduct, control, and manage electrical signals and power under specified conditions. It encompasses factors such as resistance, capacitance, power efficiency, signal integrity, and thermal performance, which are critical for the functionality and reliability of electronic devices.
Eutectic bonding: Eutectic bonding is a process that occurs when two materials are joined together using a eutectic alloy that has a lower melting point than the individual components. This technique allows for strong, reliable bonds at lower temperatures, making it particularly useful in various applications where heat-sensitive materials are involved. Eutectic bonding is essential for creating robust interconnections in micro and nano devices, enhancing both performance and reliability.
Fan-out wafer-level packaging (FOWLP): Fan-out wafer-level packaging (FOWLP) is a semiconductor packaging technology that allows for the integration of multiple chips or die in a single package, using a redistribution layer to connect the die to external pins. This technique improves performance by reducing the footprint and increasing the number of input/output (I/O) connections, while also enhancing thermal performance and reliability. FOWLP facilitates advanced applications in microelectronics by enabling smaller, lighter, and more efficient packaging solutions.
Fusion Bonding: Fusion bonding is a solid-state joining process where two materials are bonded together at the atomic level through heat, without the need for additional adhesives or fillers. This technique leverages the temperature and pressure to create a strong bond by merging the surfaces of the materials, resulting in a seamless integration that is crucial for ensuring reliability and performance in micro and nano systems.
Glass substrate: A glass substrate is a thin layer of glass used as a base for the fabrication of micro and nano devices, providing mechanical support, electrical insulation, and optical transparency. Its unique properties make it an ideal choice for various applications in wafer-level packaging techniques, allowing for effective integration of electronic components and the protection of delicate structures.
IPC Standards: IPC standards are a set of guidelines and specifications established by the Institute of Printed Circuits (IPC) to ensure the quality, reliability, and consistency of electronic manufacturing processes. These standards cover a wide range of topics, including materials, processes, and testing methods, facilitating effective communication and reducing variability in production. They play a crucial role in enhancing product performance and safety across various applications, including wafer-level packaging techniques.
JEDEC Standards: JEDEC Standards are a set of technical standards developed by the Joint Electron Device Engineering Council, primarily focused on semiconductor technology. These standards provide guidelines for the design, testing, and reliability of electronic components, including MEMS and NEMS devices. The relevance of JEDEC Standards extends to wafer-level packaging techniques and ensuring that devices meet reliability requirements throughout their lifecycle.
Package Density: Package density refers to the mass or volume of electronic components and packaging materials contained within a given area of the substrate in micro and nano electromechanical systems. This concept is crucial as it directly influences the performance, thermal management, and integration capabilities of devices at the wafer level, impacting how compactly components can be arranged without compromising functionality or reliability.
Photoresist: Photoresist is a light-sensitive material used in various microfabrication processes to create patterns on a substrate. When exposed to ultraviolet (UV) light, the chemical structure of the photoresist changes, allowing selective removal of either the exposed or unexposed areas during the development process. This property is crucial for transferring intricate designs and features onto surfaces in micro and nano electromechanical systems.
Plasma etcher: A plasma etcher is a specialized piece of equipment used in semiconductor fabrication to remove material from a substrate surface through the use of plasma. This process is critical for defining patterns in integrated circuits and microelectromechanical systems, allowing for precise control over the etching process and enabling the production of intricate structures.
Redistribution layer (rdl): The redistribution layer (RDL) is a crucial component in micro and nano electromechanical systems, primarily used in wafer-level packaging. It serves to reroute the electrical connections from the original chip pads to new locations, allowing for more efficient space utilization and improved interconnection density. By effectively managing the placement of these connections, RDL enhances the overall performance and functionality of the device while enabling advanced packaging techniques.
Sacrificial Layer Etching: Sacrificial layer etching is a process used in microfabrication where a temporary layer is selectively removed to create space or form features in the final device structure. This technique allows for the creation of complex three-dimensional shapes by initially depositing a material that can be easily etched away, thus enabling the formation of cavities or air gaps that are critical for device functionality.
Silicon Dioxide: Silicon dioxide (SiO₂) is a widely used material in micro and nano electromechanical systems (MEMS/NEMS), known for its excellent insulating properties and mechanical stability. It serves as a fundamental component in various fabrication processes, including surface and bulk micromachining, where it can act as a structural layer or sacrificial material. Its properties make it essential for creating reliable and functional devices, especially in wafer-level packaging techniques that require precise control over the substrate and device interactions.
Silicon wafer: A silicon wafer is a thin, flat piece of silicon crystal used as a substrate for the fabrication of micro and nano devices. It serves as the foundational material in the production of integrated circuits and various microelectromechanical systems (MEMS) by providing a surface for the deposition of layers and structures essential for device functionality. The silicon wafer has become critical in the historical development of semiconductor technology and plays a significant role in advanced packaging techniques.
Spin Coater: A spin coater is a device used to apply a uniform thin film of photoresist or other materials onto a substrate, typically a silicon wafer, by spinning the substrate at high speeds. This technique ensures even distribution of the liquid material due to centrifugal forces, making it essential for processes such as photolithography and wafer-level packaging.
Thermal Conductivity: Thermal conductivity is a physical property of materials that quantifies their ability to conduct heat. It plays a vital role in various applications, particularly where heat transfer is essential, influencing the efficiency and performance of devices and systems in micro and nano electromechanical systems. Understanding thermal conductivity helps in selecting appropriate materials, analyzing scaling effects, and designing effective actuation mechanisms and packaging techniques.
Thermal management: Thermal management refers to the process of controlling and regulating the temperature of a device or system to ensure optimal performance and reliability. In the context of micro and nano electromechanical systems, effective thermal management is crucial for preventing overheating, maintaining material properties, and ensuring the longevity of components, particularly during wafer-level packaging processes.
Through-silicon vias (TSVs): Through-silicon vias (TSVs) are vertical electrical connections that pass through a silicon wafer, enabling communication between different layers of integrated circuits. This technology is crucial in three-dimensional (3D) packaging, where multiple chips are stacked to enhance performance and reduce the footprint of electronic devices. TSVs facilitate shorter interconnect paths, lower power consumption, and improved signal integrity, which are essential in modern high-performance applications.
Underfill: Underfill is a type of epoxy resin used to fill the gaps between a chip and its substrate in electronic packaging, providing mechanical support and enhancing thermal and electrical performance. This material is critical in improving reliability by minimizing stresses during thermal cycling, which can lead to failures in microelectronic devices. By ensuring a more robust bond and better heat distribution, underfill plays a vital role in the longevity of advanced packaging solutions.
Wafer bonding: Wafer bonding is a process used to join two or more semiconductor wafers together to create a single structure, which can be utilized in various micro and nano devices. This technique is essential for enhancing the mechanical and electrical properties of devices, allowing for the integration of different materials and functionalities. Wafer bonding plays a critical role in the fabrication of advanced microstructures and is particularly significant in creating layered structures for applications such as sensors and microelectromechanical systems (MEMS).
Wafer-level chip scale packaging (WLCSP): Wafer-level chip scale packaging (WLCSP) is an advanced packaging technique where the die is packaged at the wafer level, enabling a smaller footprint and reduced manufacturing costs. This method eliminates the need for additional packaging steps after the wafer has been diced, allowing for higher integration density and improved performance, making it a popular choice in micro and nano electromechanical systems.